Field of the Invention
This invention relates generally to the field of graphics processors. More particularly, the invention relates to an apparatus and method for page table management.
Description of the Related Art
On existing systems, memory allocated using a malloc/free memory call is able to maintain global data coherency across CPUs and GPGPUs; and remove the maximum memory size cap by using a page fault mechanism. Certain OS modifications are required in order to support this unified memory architecture.
Page fault handling (either by CPU or GPU) is conventionally managed by a single entity (e.g. the CPU) to prevent potential page table read/write contention and the risk of memory corruption. The GPU will interrupt the CPU when a GPU-induced page fault occurs and invoke the CPU interrupt handler to resolve the page fault by performing a memory page mapping which may updated the GPU's Input Output Memory Management Unit (IOMMU) translation lookaside buffer (TLB). These types of CPU-handled GPU page faults may cause significant performance overhead to both the CPU and the GPU.